The present invention relates to interconnect semiconductor structures and, in particular to an alpha-phase W barrier layer that is formed in the trenches or vias of such interconnect structures using a low temperature/low pressure chemical vapor deposition technique, wherein tungsten hexacarbonyl, W(CO)6 is employed as the precursor or source material. The alpha-phase W barrier layer of the present invention is ultra-thin (less than 15 nm), essentially impermeable to conductive materials, exhibits good adhesion to the dielectric material and the conductive material of the interconnect structure, and it conformally and continuously covers a high aspect ratio trench (greater than 3:1 depth/width). Hence, the alpha-phase W barrier layer of the present invention can be used in many interconnect structures wherein such a barrier layer is required. This includes, but is not limited to: damascene structures, memory cell capacitors and all other wiring applications for logic, memory and input/output applications. The barrier layer of the present invention can also be used in gate stack applications between polysilicon and a metallization, i.e. conductive, layer.
In order to fabricate high performance interconnect structures for state of the art semiconductor devices, it is necessary to embed a conductive material such as Cu into a dielectric material having a trench or via formed therein. Organic as well as inorganic dielectric materials are known and are currently being employed in such applications. Examples of organic dielectrics include: polyimides, paralyne polymers, silicon polymers, i.e. polysiloxanes, diamond, diamond-like carbon and the like, while SiO2, Si3N4, silicon oxide/nitride mixtures or alternating oxide/nitride layers are known inorganic dielectrics.
While Cu is currently being developed for use in semiconductor manufacturing by the assignee herein for such applications, it exhibits a number of undesirable properties. One highly undesirable property that Cu exhibits is that it generally diffuses through the dielectric material at the moderately elevated temperatures encountered during subsequent processing steps. The out-diffusion of Cu can have a number of deleterious effects on the interconnect structure being manufactured. For example, the out-diffusion of Cu may cause short circuiting of the wires or it may degrade the performance of the MOS device.
To overcome this out-diffusion problem exhibited by Cu, a barrier layer is generally formed between Cu and the dielectric material. In prior instances, the material used in forming the barrier layer has not been compatible with the dielectric material, i.e. it does not adhere well to the dielectric material. Thus, an additional adhesion layer has been required in order to achieve satisfactory adhesion of the barrier layer material to the dielectric.
A typical prior art interconnect structure containing a dielectric, an additional adhesion layer, a barrier layer and Cu is shown in FIG. 1. Specifically, this prior art interconnect structure shown in FIG. 1 comprises a dielectric 10 having at least one trench or via formed therein, an adhesion layer 12, a barrier layer 14 and Cu region 16. The trench or via is formed in the surface of dielectric 10 using standard lithographic patterning techniques that are well known to those skilled in the art. It should be emphasized that although the various layers are shown as conformal layers in FIG. 1 in reality the layers are non-conformal since the previous prior art processing techniques used in forming the various layers are incapable of providing conformal trench coverage.
As stated above, the adhesion layer is only required when barrier layer 14 is not compatible with dielectric 10. Suitable materials for the adhesion layer include: Ti, Cr and other similar materials. The adhesion layer is formed using standard deposition techniques such as sputtering. The Cu region is formed using plating, chemical vapor deposition, plasma vapor deposition and like techniques which are also well known in the art.
The barrier layer in the prior art structure of FIG. 1 is typically composed of a metal such as Ta. The prior art barrier layers may be formed using sputtering and other known deposition techniques.
Although a wide range of materials can be employed as barrier layer 14, the prior art barrier layers do not meet all of the following requirements which are now deemed as necessary in the fabrication of interconnect structures:
(1). The barrier layer must be impermeable to Cu under the conditions to which the device will experience in further processing, as well as under operating conditions;
(2). The barrier layer must exhibit good adhesion to the dielectric comprising the interconnect structure; therefore, obviating the need for an additional adhesion layer;
(3). The barrier layer must be formed in such a manner as to comformally and continuously cover a high aspect ratio trench. By xe2x80x9chigh aspect ratioxe2x80x9d, it is meant a trench wherein the depth to width ratio is greater than 3:1;
(4). The barrier layer should be as thin as possible, so as to maximize the fraction of the cross-section of the trench which may be filled with the Cu wiring, so as to maximize wire conductivity;
(5). The barrier layer should be of uniform thickness throughout the structure, i.e. coverage of the interconnect trench should be conformal. A barrier failure will be determined by the thinnest region of the structure, non-uniformity in thickness will necessarily be wasteful of the trench cross-sectional area;
(6). The barrier layer should be made from a material that has the lowest possible resistivity so as to aide in minimizing the total wire resistivity; and
(7). The barrier layer should be resistant to oxidation so as to facilitate the filling of the remaining trench volume with Cu with a minimum of pretreatment steps or processes.
While prior art barrier layers may satisfy one or more of the above criteria, none of the barrier layers provided in prior art processes are known to satisfy all of them. Thus, there is a need to develop a new barrier layer that satisfies each and every criteria mentioned hereinabove. Such a barrier layer would be extremely useful in all semiconductor interconnect applications wherein Cu or another conductive metal is found.
One object of the present invention is to provide a barrier layer for use in interconnect trench or via structures which satisfies the above mentioned criteria listed under items 1-7.
One specific objective met by the present invention is that it provides a barrier layer that is compatible, i.e. adheres, with both the dielectric material and the conductive material so as to eliminate the need of an additional adhesion layer in interconnect structures.
A second specific objective met by the present invention is that it provides a barrier layer which is ultra-thin (less than 15 nm) and is capable of conformally covering high aspect ratio trenches or vias.
These and other aspects and advantages are achieved in the present invention by utilizing alpha-W as a barrier layer, wherein the alpha-W is formed by a low temperature/low pressure chemical vapor deposition (CVD) process using tungsten hexacarbonyl, W(CO)6, as the precursor, i.e. source material. Specifically, the barrier layer of the present invention comprises alpha-phase W which is a single phased material that is formed from W(CO)6 utilizing a low temperature/low pressure CVD process. No other phases such as xcex2-W are formed by utilizing the method of the present invention.
Another aspect of the present invention relates to a method of forming an alpha-W barrier layer on the sidewalls and bottom of a trench or via that was previously formed in a dielectric material. Specifically, the alpha-W barrier layer is formed in the present invention by depositing a conformal layer of alpha-W having a thickness of less than 15 nm on the sidewalls and bottom of a trench or via region previously formed in a dielectric material, wherein said deposition is carried out by chemical vapor deposition (CVD) using W(CO)6 as a source material.
A still further aspect of the present invention relates to a structure comprising at least one layer of a semiconducting, e.g. polysilicon, or dielectric material having a layer of alpha-W over a portion of said semiconducting or dielectric material; and a conductive material formed over said alpha-W layer. The alpha-W is formed over the material in accordance with the method described hereinabove in forming the alpha-W barrier layer.
A yet further aspect of the present invention relates to interconnect structures that contain the alpha-W barrier layer of the present invention inside the trench or via structure. Specifically, the interconnect structure of the present invention comprises one or more layers of a dielectric material having at least one trench or via region therein; a barrier layer of the alpha-W covering the sidewalls and the bottom of the at least one trench or via region, wherein said alpha-W barrier layer is a continuous single phased material having a thickness of less than 15 nm; and a conductive material formed over said alpha-W barrier layer in said at least one trench or via region. Vias may also be formed in a respective dielectric extending from the bottom of a trench to an interconnect wiring trench below.
Suitable interconnect structures that are contemplated in the present invention include, but are not limited to: memory cell capacitors including plate capacitors, crown capacitors, stack capacitors and other like capacitors; damascene structures including dual and single; multiple wiring levels containing a plurality of vias and metal lines; and other like interconnect structures.